-------------------------------------------------------------------------------
-- alu_rtl.vhd
-------------------------------------------------------------------------------
--
-- This file is part of SKUMLI.
-- Copyright (C) 2011 Davide Giuseppe Monaco (black.ralkass@gmail.com)
--
-- SKUMLI is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- SKUMLI is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with SKUMLI.  If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
architecture rtl of alu is
begin -- rtl
-------------------------------------------------------------------------------
  main: process (a, b, op)

    variable x : std_logic_vector(N - 1 downto 0); 
    variable z : std_logic;

  begin -- main

    case op is

      when "00" =>      -- add
        x := a + b;
        z := '0';

      when "01" =>      -- sub
        x := a - b;

        if x = (x'range => '0') then
          z := '1';
        else
          z := '0';
        end if;

      when "11" =>       -- sgt
        if a > b then
          x(N - 1) := '1';
        else
          x(N - 1) := '0';
        end if;
          
        x(N - 2 downto 0) := (others => '0');
        
        z := '0';

      when "10" =>       -- slt
        if a < b then
          x(N - 1) := '1';
        else
          x(N - 1) := '0';
        end if;
          
        x(N - 2 downto 0) := (others => '0');
        
        z := '0';

      when others =>
        x := (others => '0');
        z := '0';

    end case;

    dout <= x;
    zero <= z;

  end process main;
-------------------------------------------------------------------------------
end rtl;
